Datapath

ALU

Regfiles

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_ARITH.all;

use IEEE.STD_LOGIC_UNSIGNED.all;

use WORK.GEN_DEFS.all;

entity regfiles is

port(

ADDRESSR: in std_logic_vector(3 downto 0);

clk: in std_logic;

nWER: in std_logic;

ACCR: in std_logic_vector(3 downto 0);

DATAR: out std_logic_vector(3 downto 0)

);

end regfiles;

architecture Behavior of regfiles is

begin

Read_Write:

process (clk)

variable reg_array: REGFILE:= (others => "0000");

variable index: integer range 0 to 15;

begin

if clk'Event and clk='1' then

if nWER = '1' then reg_array(CONV_INTEGER(ADDRESSR)):= ACCR; -- memory write

end if;

end if;

DATAR <= reg_array(index);

end process;

end Behavior;

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_ARITH.all;

use IEEE.STD_LOGIC_UNSIGNED.all;

use WORK.GEN_DEFS.all;

entity ALU is

port(

CURR_ACC: in std_logic_vector(3 downto 0);

CURR_IR: in std_logic_vector(3 downto 0);

CURR_CARRY: in std_logic;

CURR_ZERO: in std_logic;

ALU_OP: in std_logic_vector(2 downto 0);

NEXT_ACC: out std_logic_vector(3 downto 0);

NEXT_CARRY: out std_logic;

NEXT_ZERO: out std_logic

);

end ALU;

architecture Behavior of ALU is

begin

PerformOperation:

process (CURR_ACC, CURR_IR, CURR_CARRY, CURR_ZERO, ALU_OP)

variable sm: std_logic_vector(4 downto 0);

begin

case ALU_OP is

when PASS_OP => NEXT_ACC <= CURR_IR;

NEXT_CARRY <= CURR_CARRY;

NEXT_ZERO <= CURR_ZERO;

when ADD_OP => sm:= ('0' & CURR_ACC) + ('0' & CURR_IR) + ("0000" & CURR_CARRY);

NEXT_ACC <= sm(3 downto 0);

NEXT_CARRY <= sm(4);

if sm(3 downto 0) = "0000" then

NEXT_ZERO <= '1';

else

NEXT_ZERO <= '0';

end if;

when XOR_OP => NEXT_ACC <= CURR_ACC xor CURR_IR;

NEXT_CARRY <= CURR_CARRY;

NEXT_ZERO <= CURR_ZERO;

when AND_OP => NEXT_ACC <= CURR_ACC and CURR_IR;

NEXT_CARRY <= CURR_CARRY;

NEXT_ZERO <= not((CURR_ACC(3) and CURR_IR(3)) or

(CURR_ACC(2) and CURR_IR(2)) or

(CURR_ACC(1) and CURR_IR(1)) or

(CURR_ACC(0) and CURR_IR(0)));

when SET_CARRY_OP => NEXT_ACC <= CURR_ACC;

NEXT_CARRY <= '1';

NEXT_ZERO <= CURR_ZERO;

when CLR_CARRY_OP => NEXT_ACC <= CURR_ACC;

NEXT_CARRY <= '0';

NEXT_ZERO <= CURR_ZERO;

when others => NEXT_ACC <= CURR_ACC;

NEXT_CARRY <= CURR_CARRY;

NEXT_ZERO <= CURR_ZERO;

end case;

end process;

end Behavior;

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_ARITH.all;

use IEEE.STD_LOGIC_UNSIGNED.all;

entity Datapath is

port(

-- Control Unit Interface

CLK: in std_logic;

RESET: in std_logic;

WRITE: in std_logic;

READ: in std_logic;

JUMP_PC: in std_logic;

INC_PC: in std_logic;

LD_IR: in std_logic;

LD_IR_LSN: in std_logic;

ALU_OP: in std_logic_vector(2 downto 0);

IR_DATA: out std_logic_vector(7 downto 0);

Z_ST: out std_logic;

C_ST: out std_logic;

-- External Memory Interface

ADDRESS: out std_logic_vector(6 downto 0);

DATA: in std_logic_vector(7 downto 0);

nCSB: out std_logic;

-- nWEB: out std_logic;

nOEB: out std_logic;

-- from fifo

Qf: in std_logic_vector(3 downto 0);

full: in std_logic;

rdf: out std_logic;

rfifo: in std_logic;

rdfcu: in std_logic;

fullcu: out std_logic

);

end Datapath;

architecture Behavior of Datapath is

component ALU is

port(

CURR_ACC: in std_logic_vector(3 downto 0);

CURR_IR: in std_logic_vector(3 downto 0);

CURR_CARRY: in std_logic;

CURR_ZERO: in std_logic;

ALU_OP: in std_logic_vector(2 downto 0);

NEXT_ACC: out std_logic_vector(3 downto 0);

NEXT_CARRY: out std_logic;

NEXT_ZERO: out std_logic

);

end component ALU;

component regfiles is

port(

ADDRESSR: in std_logic_vector(3 downto 0);

clk: in std_logic;

nWER: in std_logic;

ACCR: in std_logic_vector(3 downto 0);

DATAR: out std_logic_vector(3 downto 0)

);

end component regfiles;

signal IR, NEXT_IR: std_logic_vector(7 downto 0); -- Instruction Register

signal ACC, NEXT_ACC: std_logic_vector(3 downto 0); -- ACCumulator

signal Z, NEXT_Z: std_logic; -- Z flag

signal C, NEXT_C: std_logic; -- C flag

signal PC, NEXT_PC: std_logic_vector(6 downto 0); -- Program Counter

signal ACCRNEXT, DATARNEXT, ADDRESSRNEXT: std_logic_vector(3 downto 0);

signal IRMUX: std_logic_vector(3 downto 0);

signal rdf_dp,full_dp: std_logic;

begin

-- Memory Control Signals

nCSB <= '0';

nOEB <= not READ;

-- Address Bus (Multiplexer M1)

ADDRESS <= PC;

-- Data to PC (Multiplexer M2 and SM)

NEXT_PC <= IR(6 downto 0) when JUMP_PC = '1' else PC + 1 when INC_PC = '1' else PC;

-- Data to IR

NEXT_IR <= DATA when LD_IR = '1' else (IR(7 downto 4) & DATARNEXT)

when LD_IR_LSN = '1' else IR;

--REG ADDRES

ADDRESSRNEXT <=IR(3 DOWNTO 0);

-- FROM ALU

IRMUX <= Qf when rfifo = '1' else IR(3 downto 0);

-- State signals to Control Unit

Z_ST <= Z;

C_ST <= C;

IR_DATA <= IR;

-- Datapath registers implementation

Registers:

process (CLK, RESET)

begin

if RESET = '1' then -- asynchronous reset

PC <= "0000000";

IR <= "00000000";

ACC <= "0000";

Z <= '0';

C <= '0';

elsif CLK'Event and CLK = '1' then

PC <= NEXT_PC;

IR <= NEXT_IR;

ACC <= NEXT_ACC;

Z <= NEXT_Z;

C <= NEXT_C;

end if;

end process;

rdf <= rdf_dp;

rdf_dp <= rdfcu;

fullcu <= full_dp;

full_dp <= full;

-- ALU connections

U0:

component ALU

port map(

CURR_ACC => ACC,

CURR_IR => IRMUX,

CURR_CARRY => C,

CURR_ZERO => Z,

ALU_OP => ALU_OP,

NEXT_ACC => NEXT_ACC,

NEXT_CARRY => NEXT_C,

NEXT_ZERO => NEXT_Z

);

U1:

component regfiles

port map(

ADDRESSR => ADDRESSRNEXT,

clk => CLK,

nWER => WRITE,

ACCR => NEXT_ACC,

DATAR => DATARNEXT

);

end Behavior;

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Дата добавления: 2015-08-31