GnomeMCU

ControlUnit

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use WORK.GEN_DEFS.all;ControlUnit

entity ControlUnit is

port(

CLK: in std_logic;

RESET: in std_logic;

IR_DATA: in std_logic_vector(7 downto 0);

Z_ST: in std_logic;

C_ST: in std_logic;

WRITE: out std_logic;

READ: out std_logic;

JUMP_PC: out std_logic;

INC_PC: out std_logic;

LD_IR: out std_logic;

LD_IR_LSN: out std_logic;

ALU_OP: out std_logic_vector(2 downto 0);

-- fofo--

rdf: out std_logic;

rfifo: out std_logic;

full: in std_logic

);

end ControlUnit;

architecture Behavior of ControlUnit is

type MachineStates is (I_F, I_D, E_X);

signal STATE, NEXT_STATE: MachineStates;

begin

-- Control Unit is implemented as Mealy FSM

StateRegister:

process (CLK)

begin

if CLK'Event and CLK = '1' then

if RESET = '1' then

STATE <= I_F;

else

STATE <= NEXT_STATE;

end if;

end if;

end process;

Transition_and_Output_Function:

process (CLK)

begin

READ <= '0';

WRITE <= '0';

JUMP_PC <= '0';

INC_PC <= '0';

LD_IR <= '0'

LD_IR_LSN <= '0';

ALU_OP <= "000";

rfifo <= '0';

rdf <= '0';

case STATE is

when I_F => READ <= '1';

INC_PC <= '1';

LD_IR <= '1';

NEXT_STATE <= I_D;

when I_D => if IR_DATA(7 downto 4) = ADD_DIR or IR_DATA(7 downto 4) = XOR_DIR or

IR_DATA(7 downto 4) = LOAD_DIR or IR_DATA(7 downto 4) = TEST_DIR then

LD_IR_LSN <= '1';

end if;

NEXT_STATE <= E_X;

when E_X => if IR_DATA = CLEAR_C then

ALU_OP <= CLR_CARRY_OP;

end if;

if IR_DATA = SET_C then

ALU_OP <= SET_CARRY_OP;

end if;

if IR_DATA = SKIP_C then

if C_ST = '1' then

INC_PC <= '1';

end if;

end if;

if IR_DATA = SKIP_Z then

ALU_OP <= PASS_OP;

if Z_ST = '1' then

INC_PC <= '1';

end if;

end if;

if IR_DATA(7 downto 4) = LOAD_IMM or IR_DATA(7 downto 4) = LOAD_DIR then

ALU_OP <= PASS_OP;

end if;

if IR_DATA(7 downto 4) = ADD_IMM or IR_DATA(7 downto 4) = ADD_DIR then

ALU_OP <= ADD_OP;

end if;

if IR_DATA(7 downto 4) = STORE_DIR then

WRITE <= '1';

end if;

if IR_DATA(7 downto 4) = XOR_DIR then

ALU_OP <= XOR_OP;

end if;

if IR_DATA(7 downto 4) = TEST_DIR then

ALU_OP <= AND_OP;

end if;

if IR_DATA(7) = JUMP then

JUMP_PC <= '1';

ALU_OP <= PASS_OP;

end if;

if IR_DATA(7 downto 0) = read_fifo then

rfifo <= '1';

rdf <= '1';

ALU_OP <= PASS_OP;

end if;

NEXT_STATE <= I_F;

end case;

end process;

end Behavior;

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity GnomeMCU is

port(

CLOCK: in std_logic;

RESET: in std_logic;

-- Memory interface

ADDRESS: out std_logic_vector(6 downto 0);

DATA: in std_logic_vector(7 downto 0);

Qf: in std_logic_vector(3 downto 0); --add

nCSB: out std_logic;

nOEB: out std_logic;

fullf: in std_logic; --add

rdf: out std_logic --add

);

end GnomeMCU;

architecture Structure of GnomeMCU is

component ControlUnit is

port(

CLK: in std_logic;

RESET: in std_logic;

IR_DATA: in std_logic_vector(7 downto 0);

Z_ST: in std_logic;

C_ST: in std_logic;

WRITE: out std_logic;

READ: out std_logic;

JUMP_PC: out std_logic;

INC_PC: out std_logic;

LD_IR: out std_logic;

LD_IR_LSN: out std_logic;

ALU_OP: out std_logic_vector(2 downto 0);

-- add potr

-- fofo--

rdf: out std_logic;

rfifo: out std_logic;

full: in std_logic

);

end component ControlUnit;

component Datapath is

port(

-- Control Unit Interface

CLK: in std_logic;

RESET: in std_logic;

WRITE: in std_logic;

READ: in std_logic;

JUMP_PC: in std_logic;

INC_PC: in std_logic;

LD_IR: in std_logic;

LD_IR_LSN: in std_logic;

ALU_OP: in std_logic_vector(2 downto 0);

IR_DATA: out std_logic_vector(7 downto 0);

Z_ST: out std_logic;

C_ST: out std_logic;

-- External Memory Interface

ADDRESS: out std_logic_vector(6 downto 0);

DATA: in std_logic_vector(7 downto 0);

nCSB: out std_logic;

nOEB: out std_logic;

Qf: in std_logic_vector(3 downto 0);

full: in std_logic;

rdf: out std_logic;

rfifo: in std_logic;

rdfcu: in std_logic;

fullcu: out std_logic

);

end component Datapath;

signal IR_DATA_BUS: std_logic_vector(7 downto 0);

signal Z_ST_NET, C_ST_NET, WRITE_NET, READ_NET, JUMP_PC_NET, INC_PC_NET,

LD_IR_NET, LD_IR_LSN_NET: std_logic;

signal ALU_OP_BUS: std_logic_vector(2 downto 0);

signal fullfnet, rdfnet, clkfnet: std_logic;-- gnom

signal Qfnet: std_logic_vector(3 downto 0); -- gnom

signal rdfcunet,rfifocunet,fullcunet: std_logic; --cu

begin

U0: component Datapath

port map(

-- External memory interface

ADDRESS => ADDRESS,

DATA => DATA,

nCSB => nCSB,

nOEB => nOEB,

-- Control unit connections

CLK => CLOCK,

RESET => RESET,

WRITE => WRITE_NET,

READ => READ_NET,

JUMP_PC => JUMP_PC_NET,

INC_PC => INC_PC_NET,

LD_IR => LD_IR_NET,

LD_IR_LSN => LD_IR_LSN_NET,

ALU_OP => ALU_OP_BUS,

IR_DATA => IR_DATA_BUS,

Z_ST => Z_ST_NET,

C_ST => C_ST_NET,

Qf => Qf,

full => fullf,

rdf => rdf,

rfifo => rfifocunet,

rdfcu => rdfcunet,

fullcu => fullcunet

);

U1: component ControlUnit

port map(

CLK => CLOCK,

RESET => RESET,

-- Datapath connections

IR_DATA => IR_DATA_BUS,

Z_ST => Z_ST_NET,

C_ST => C_ST_NET,

WRITE => WRITE_NET,

READ => READ_NET,

JUMP_PC => JUMP_PC_NET,

INC_PC => INC_PC_NET,

LD_IR => LD_IR_NET,

LD_IR_LSN => LD_IR_LSN_NET,

ALU_OP => ALU_OP_BUS,

rdf => rdfcunet,

rfifo => rfifocunet,

full => fullcunet

);

end Structure;

Дата добавления: 2015-08-31